This title carefully details design tools and techniques for high-performance ASIC design. Using these techniques, the performance of ASIC designs can be improved by two to three times. Important topics include: improving performance through microarchitecture; timing-driven floorplanning; controlling and exploiting clock skew; high performance latch-based design in an ASIC methodology; automatically identifying and synthesizing complex logic gates; automated cell sizing to increase performance and reduce power; and controlling process variation. These techniques are illustrated by designs running two to three times the speed of typical ASICs in the same process generation.
